In a conventional LSI, the elements are integrated in the two-dimensional plane on a silicon substrate. However, the storage capacity of a memory can be increased only by downsizing (micropatterning) each element. Recently, however, the micropatterning has also become difficult in terms of cost and technique.
To solve the above-described problem, there has been proposed an idea for three-dimensionally stacking memory layers and batch-processing them to manufacture a three-dimensionally stacked memory. In addition, as the collectively-processed-type three-dimensionally stacked memory (bit cost scalable (BiCS)), a pipe-type NAND flash memory (p-BiCS) has been proposed in which U-shaped memory strings are formed in the stacking direction. In the pipe-type NAND flash memory, one memory string is formed by a pair of silicon pillars and a pipe that connects them at the lower end. More specifically, memory cell transistors are arranged at the intersections between the silicon pillars and a plurality of stacked word lines. Additionally, select transistors are arranged at the intersections between each of a pair of silicon pillars and two select gates. One of the two select transistors is connected to a bit line, and the other is connected to a source line.